The present invention relates to electronic devices, and, more particularly, to semiconductor devices useful in digital delay lines.
Designers of electronic systems often need to adjust the relative timing of various events within a system during operation and they use delay lines for such timing adjustments. For example, delay lines may be used to adjust sampling times in high-speed analog systems or to avoid possible pulse collisions in asynchronous digital systems. Various delay line products are available, both analog and digital. For example, the DS1000 family of five-tap delay lines manufactured by Dallas Semiconductor Corporation, which can reproduce an input digital pulse with delays selectable from 5 nanoseconds (nsec) to 500 nsec. Further products with delay line enhancements, such as programmable delays, are also available. These programmable delay lines permit the delay time to be varied by signals generated within the system during operation.
Delay lines commonly provide a capacitor, a current source for charging the capacitor, a reset path for rapid discharge of the capacitor, and a threshold detector. The typical digital delay line operates as follows: a pulse to be delayed is input and first disconnects the reset path and thus starts the current source charging the capacitor. The size of the capacitor and the amperage of the current source determine the rate at which the capacitor voltage increases. Then when the capacitor voltage reaches the trigger level of the threshold detector, an output pulse is generated, and the reset path quickly discharges the capacitor. Programmable delays can be achieved by control of the amperage of the current source. Indeed, if the current source has a current of I, the capacitor a capacitance of C, and the threshold detector triggers at voltage V, then the delay time is essentially VC/I.
Aspects of known delay lines can be found in the following articles: M. Bazes, A Novel Precision MOS Synchronous Delay Line, 20 IEEE J. Sol. St. Cir. 1265 (1985) and Johnson and Hudson, A Variable Delay Line PLL for CPU-Coprocessor Synchronization, 23 IEEE J. Sol. St. Cir. 1218 (1988).
Known delay lines have problems which include the laser trimmable fuses used to select the delays available. Laser trimming is a time consuming process and prevents packaging a delay line integrated circuit until the delays have been programmed by fuse blowing. Further, laser trimming fuses prior to packaging leads to a shift (offset) of the programmed delays caused by the packaging itself. See U.S. Pat. No. 4,894,791 which describes a delay mesurement of a few die while still in wafer form followed by computation of a desired delay and then laser fuse blowing in all of the die to establish the desired delays. This patent also mentions in passing that EEPROM or UVPROM could be used in place of laser blown fuses.
Known delay lines also have the problem of drift of delay time with temperature and power supply variations. Increases in temperature typically lead to increases in resistance and capacitance, and decreases in power supply voltage typically make semiconductor devices run more slowly. These variations require a delay line to have compensation circuitry for maintaining the delay time such as by adjusting the threshold voltage of the voltage detector in the ease of a current charging a capacitor. However, this compensation can lead to involved circuitry in order to be compatible with non-laser trimming.
The present invention provides for an electrically trimmable programmable delay line without the use of fuses and compensates for packaging delay offset. Preferred embodiments use floating gate transistors in place of fuses, and such transistors may be programmed after packaging of the integrated circuit. Further embodiments include electrically erasable and reprogrammable floating gate transistors, and delay lines of cells with programmed loads for variance of the delays. The invention further provides temperature and power supply voltage compensation compatible with electrically trimming by adjusting capacitor charge-up currents.